For decades, the semiconductor industry has followed a remarkably simple formula: make transistors smaller, fit more of them onto a chip, and computers become faster and more efficient.
That principle is commonly known as Moore's Law.
But there is a problem. We are running out of room.
Researchers at the University of Illinois Urbana-Champaign recently demonstrated a new method of building silicon chips that suggests the future of computing might no longer be about making chips smaller.
Instead, we may start building them upwards.
And that could have major consequences for the processors inside future laptops, workstations and AI systems.
What exactly is Moore's Law?
In 1965, Intel co-founder Gordon Moore observed that the number of components that manufacturers could economically place on an integrated circuit was increasing extremely quickly.
The idea eventually became associated with transistor density roughly doubling every couple of years.
It isn't a law of physics. It became more like a target that the semiconductor industry kept managing to hit.
Smaller transistors allowed manufacturers to put increasingly complex CPUs and GPUs into roughly the same amount of physical space.
More transistors meant more processing capability.
And smaller manufacturing processes generally helped reduce the amount of energy required to perform that processing.
For decades, it worked astonishingly well.
But transistors have now become extremely small.
At some point, you cannot simply keep shrinking structures indefinitely.
Researchers at Illinois point out that transistor dimensions are increasingly constrained by the properties of silicon itself and eventually by quantum mechanics. In other words: we are beginning to encounter limits imposed by physics rather than manufacturing capability alone.
So what happens when we can no longer keep making everything smaller?
Stop building smaller. Start building upwards.
One solution sounds surprisingly obvious.
If there isn't enough room horizontally, use the third dimension.
Modern processors are traditionally built primarily as extremely complicated two-dimensional arrangements of transistors. There are already plenty of forms of 3D packaging in today's computers — including stacked memory and technologies such as 3D V-Cache — but these generally involve manufacturing different dies or wafers before connecting them together.
The Illinois researchers are working on something considerably more ambitious: monolithic 3D integration.
Instead of manufacturing complete chips separately and stacking them afterwards, transistor layers are fabricated sequentially on top of each other.
Think of the difference between expanding a city with more suburbs and replacing those suburbs with skyscrapers.
The researchers demonstrated up to three vertically integrated transistor layers and used them to construct logic circuits and SRAM memory cells. Their process uses ultrathin single-crystalline silicon membranes measuring 10 nanometres or less.
More importantly, those layers can potentially be connected much more densely than separately manufactured chips.
The University of Illinois estimates monolithic integration could enable 10 to 100 times denser vertical connections between layers compared with conventional 3D integration techniques.
That is important because modern computing isn't only limited by how fast an individual transistor can switch.
Moving data around is increasingly part of the problem.
The processor doesn't just need to calculate. It needs to communicate.
This becomes particularly interesting for AI workloads.
A CPU or GPU might contain enormous amounts of computing capability, but those processing units constantly need data.
Moving information between processing cores, cache, memory and other parts of the system takes time — and consumes power.
By placing components vertically above each other rather than far apart across a chip, electrical connections can become significantly shorter.
Shorter connections potentially mean:
- higher communication bandwidth;
- lower latency;
- lower energy consumption;
- greater computing density.
That combination is extremely attractive for CPUs, GPUs and especially AI accelerators.
It also highlights something we have been seeing for years at SKIKK: computer performance is increasingly about the complete architecture rather than one specification.
A faster CPU alone doesn't necessarily create a faster computer.
Memory bandwidth matters. Cache matters. Storage matters. Cooling matters. Power limits matter. And increasingly, how efficiently the different parts of a processor can communicate matters.
3D chip architectures could take this principle right down to the transistor level.
If stacking chips is such a good idea, why haven't we already done it?
Heat.
Or, more specifically, heat during manufacturing.
Producing conventional high-performance silicon devices normally involves temperatures approaching 1,000 °C.
That's fine when you're manufacturing the first transistor layer.
It becomes a serious problem when you try to manufacture another layer directly on top of circuitry that already exists. The metal connections in the existing layer cannot tolerate those manufacturing temperatures.
Once the first circuitry is completed, the accepted thermal budget for additional layers is around 400 °C.
The Illinois team developed a way around that problem.
Instead of forming the crystalline silicon directly on top of the existing circuitry, they manufacture extremely thin single-crystalline silicon membranes separately and transfer them onto the wafer.
The bonding process requires temperatures of no more than around 200 °C, while subsequent processing remains within the required 400 °C thermal budget.
That allows another high-performance silicon transistor layer to be added without destroying the circuitry underneath it.
And then potentially another.
And another.
So, is Moore's Law dead?
Not necessarily.
Perhaps the more interesting conclusion is that Moore's Law may survive by changing what "scaling" means.
For decades:
Smaller transistors = more transistors per chip.
In the future, it could increasingly become:
More layers = more transistors in the same footprint.
Instead of continuously reducing the size of individual transistors, semiconductor manufacturers could increase density vertically.
We have already seen a similar transition elsewhere in computing.
NAND flash storage moved aggressively towards 3D architectures years ago. Modern processors increasingly use chiplets. High Bandwidth Memory stacks memory dies. AMD has commercially deployed vertically stacked cache.
The direction of travel is clear: the computer industry is becoming increasingly comfortable moving away from one enormous flat piece of silicon.
Monolithic 3D integration could take that concept considerably further.
Don't expect a three-storey CPU in your laptop next year
There is an important distinction between impressive semiconductor research and mass-market production.
The Illinois team demonstrated three tiers containing hundreds of transistors per layer with very high device yields. The underlying Nature paper reports wafer-scale integration, sub-10-nanometre alignment between tiers and transistor performance approaching conventional high-performance silicon devices.
Those are important results.
But a modern consumer processor contains billions of transistors.
Going from a successful academic demonstration to economical mass production inside one of the world's most advanced semiconductor fabs is an enormous engineering challenge.
The research team is now working toward transferring the process to an industrial semiconductor foundry. The Nature paper itself describes the technology as particularly promising for research and low-volume prototyping at this stage.
So this is not an announcement of the processor that will power next year's SKIKK laptops.
It is something much more fundamental: a demonstration of one possible way processors could continue evolving once conventional transistor scaling becomes increasingly difficult.
What could this mean for future laptops?
Potentially, quite a lot.
Higher computing density could eventually allow substantially more processing capability within the same physical chip area.
Shorter connections could reduce the energy spent moving data around.
That creates the possibility of processors that are:
Faster without becoming proportionally larger.
More power-efficient at the same performance level.
Better suited to extremely data-intensive workloads such as local AI.
For laptops in particular, efficiency improvements can be every bit as important as raw performance.
You can always feed a desktop processor more electricity and attach a larger heatsink.
A laptop has fixed physical limitations.
There is only so much cooling capacity, battery capacity and physical space available.
The most interesting future processor therefore isn't necessarily the one that consumes 200 watts and wins a benchmark.
It may be the processor capable of doing today's 200-watt workload at 50 watts.
Technologies such as monolithic 3D integration could eventually help move us in that direction.
The end of Moore's Law — or its next chapter?
For more than half a century, semiconductor progress has largely meant shrinking things.
That strategy isn't suddenly over. Chip manufacturers will continue improving transistor designs and fabrication processes wherever physics and economics allow it.
But the future appears increasingly unlikely to depend on transistor size alone.
Chiplets.
Stacked cache.
3D memory.
Advanced packaging.
Specialised accelerators.
And perhaps, eventually, several layers of high-performance silicon transistors constructed directly on top of each other.
The computer chip of the future may not simply be smaller.
It may be taller.
And if research such as this can successfully make the transition from the laboratory to industrial semiconductor manufacturing, Moore's Law might not be approaching its end at all.
We might simply have been looking at it in two dimensions.
This article was inspired by research from Qing Cao and colleagues at the University of Illinois Urbana-Champaign. Their study, “Monolithic three-dimensional integration of silicon transistors”, was published in Nature in May 2026.